Single-ended sensing techniques are used in various circuit applications involving both memory and logic, including, for example, read-only memory (ROM) and register file (REGFILE) memory. In a typical memory circuit application, numerous memory cells (e.g., up to about 512) are connected to a common line, often referred to as a bit line. A memory circuit typically includes a plurality of bit lines and corresponding memory cells coupled thereto. As the number of memory cells connected to a given bit line in the memory circuit increases, the time for a single memory cell to charge and/or discharge the bit line increases accordingly. This is due primarily to the increased capacitance on the bit line attributable to the memory cells connected thereto.
In many cases, particularly single-ended sensing applications, the logical state of a selected memory cell in a memory circuit is sensed, for example during a read operation, by an inverter connected to a corresponding bit line associated with the selected memory cell. A local access time of the memory circuit is defined primarily by the time it takes for the voltage on the bit line to reach a switching point of the sensing inverter. Therefore, since it is desirable to minimize access time in the memory circuit, it is beneficial to reduce the time it takes for the voltage on the bit line to reach the switching point of the sensing inverter.
One known technique for reducing the time it takes for the voltage on the bit line to reach the switching point of the inverter is to employ larger memory cells having increased gain capable of more quickly driving (e.g., charging or discharging) the corresponding bit lines. However, using larger memory cells undesirably increases the area and the power consumed by the memory cell, and thereby increases the cost of the memory circuit. Access time of the memory circuit may also be reduced by using a differential sensing approach, wherein bit line pairs and corresponding differential sensing circuits are used to read the respective logic states of memory cells. However, the added size and complexity of a differential sensing arrangement renders such an approach undesirable compared to a single-ended sensing methodology.
Accordingly, there exists a need for an improved single-ended sensing arrangement for use in a memory circuit which does not suffer from one or more of the problems exhibited by conventional single-ended sensing methodologies.